In the design of an analog circuit, techniques of simulating an analog property using a simulator such as SPICE are conventionally known.
Meanwhile, in the design of a digital circuit, an accurate delay time period can also be acquired by executing a simulation using a simulator such as SPICE (see, e.g., International Patent Publication No. 2004-501438) (hereinafter, “first conventional technique”). However, with techniques such as the first conventional technique, a problem arises in that a tremendous amount of time is necessary to execute a simulation for each cell in a circuit under design.
A technique is known of identifying a delay time period and an output-through (a time period necessary for an output voltage output by a cell to rise (or fall)), for each cell used in design employing a simulator such as SPICE, and storing the delay time period and the output-through as a library. The delay time period of each cell in the circuit under design is calculated by referring to the library (see, e.g., Japanese Laid-Open Patent Publication No. H10-198720) (hereinafter, “second conventional technique”).
It is known that the delay time period of a path in a circuit under design is calculated by totaling delay time periods of cells that constitute the path.
However, with the second conventional technique, load resistance (such as, for example, wiring resistance) and load capacitance (such as wiring capacitance, and an input capacitance for a downstream cell) of the output of each cell are substituted by lumped constant capacitance, and temporal variation of an output voltage is calculated using SPICE by supplying temporal variation of an input voltage to a circuit model.
The values of the load resistance and the load capacitance differ among cells depending on the layout of the circuit under design and therefore, a problem arises in that an error occurs for the delay time period compared to the case where the first conventional technique is used. In addition, the output voltage value is calculated using only the value of the lumped constant capacitance and therefore, the transient response by R (load resistance) and C (load capacitance) is approximated to a straight line. Therefore, another problem arises in that another error is generated for the delay time period compared to the case where the first conventional technique is used. In addition, when the first conventional technique is used, the above problem of a tremendous amount of time being consumed arises.
When the second conventional technique is used especially in recent processing enabling smaller dimensions, error between the delay time periods acquired by the first and the second conventional techniques becomes conspicuous with the lower voltage, the higher integration, and the higher speed. Therefore, another problem arises in that the effects of error in the delay time period can no longer be disregarded.